1. Field of the Invention
Present invention relates to logic circuitry. In particular, the present invention relates to a domino logic circuit.
2. Background of the Related Art
In semiconductor devices, the operational frequency of the devices are constantly increasing. The increasing operational frequency due to faster clock rates lessens the time for signal evaluation. Domino logic circuits increase the speed of logic circuits. A conventional domino logic circuit includes two parts, a dynamic circuit and a static circuit coupled to the dynamic circuitry. The dynamic circuitry pre-charges an output node high when a clock signal is low and lets the input data signals cause the output to evaluate low when the clock signal is high. The dynamic circuitry is often an N-type metal oxide semiconductor (NMOS) pull-down circuitry (alternatively it can be a pull-up circuitry) that is operable to pull-down the level of a relatively weakly held pre-charged circuit node. The speed of a conventional domino logic circuit is limited by the time it takes to pre-charge the dynamic circuit node and pull-down the weakly held pre-charged node.
One solution to this problem is to reduce the physical size of the circuit elements and reduce the threshold voltages of transistors within the circuit. Unfortunately, reducing transistor threshold voltage and smaller geometry results in a higher sub-threshold leakage current in the transistors. In addition, the low threshold voltages, coupled with faster signal edges and greater noise coupling due to smaller geometry, contribute to increasingly substantial noise problems.
For instance, the voltage on a dynamic node can be degraded due to charge sharing, coupling noise, and/or charge leakage. Furthermore, supply voltage scaling requires the transistor threshold voltage to reduce in order to preserve the speed of the devices, but results in logic circuits that are more sensitive to noise.
These and other disadvantages exist in conventional circuitry.